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19-3576; Rev 0; 5/05
8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs
General Description
The MAX1302/MAX1303 multirange, low-power, 16-bit, successive-approximation, analog-to-digital converters (ADCs) operate from a single +5V supply and achieve throughput rates up to 115ksps. A separate digital supply allows digital interfacing with 2.7V to 5.25V systems using the SPITM-/QSPITM-/MICROWIRETM-compatible serial interface. Partial power-down mode reduces the supply current to 1.3mA (typ). Full power-down mode reduces the power-supply current to 1A (typ). The MAX1302 provides eight (single-ended) or four (true differential) analog input channels. The MAX1303 provides four (single-ended) or two (true differential) analog input channels. Each analog input channel is independently software programmable for seven single-ended input ranges (0 to +VREF/2, -VREF/2 to 0, 0 to +VREF, -VREF to 0, VREF/4, VREF/2, and VREF), and three differential input ranges (VREF/2, VREF, 2 x VREF). An on-chip +4.096V reference offers a small convenient ADC solution. The MAX1302/MAX1303 also accept an external reference voltage between 3.800V and 4.136V. The MAX1302 is available in a 24-pin TSSOP package and the MAX1303 is available in a 20-pin TSSOP package. Each device is specified for operation from -40C to +85C.
Features
Software-Programmable Input Range for Each Channel Single-Ended Input Ranges 0 to +VREF/2, -VREF/2 to 0, 0 to +VREF, -VREF to 0, VREF/4, VREF/2, and VREF Differential Input Ranges VREF/2, VREF, and 2 x VREF Eight Single-Ended or Four Differential Analog Inputs (MAX1302) Four Single-Ended or Two Differential Analog Inputs (MAX1303) 6V Overvoltage Tolerant Inputs Internal or External Reference 115ksps Maximum Sample Rate Single +5V Power Supply 20-/24-Pin TSSOP Package
MAX1302/MAX1303
Ordering Information
PART MAX1302AEUG* MAX1302BEUG* MAX1303AEUP* MAX1303BEUP TEMP RANGE PINCHANNELS PACKAGE 8 8 4 4
-40C to +85C 24 TSSOP -40C to +85C 24 TSSOP -40C to +85C 20 TSSOP -40C to +85C 20 TSSOP
Applications
Industrial Control Systems Data-Acquisition Systems Avionics Robotics
*Future product--contact factory for availability.
Pin Configurations
TOP VIEW
AVDD1 1 CH0 2 CH1 3 CH2 4 CH3 5 CH4 6 CH5 7 CH6 8 CH7 9 CS 10 DIN 11 SSTRB 12 24 AGND1 23 AGND2 22 AVDD2 21 AGND3
MAX1302
20 REF 19 REFCAP 18 DVDD 17 DVDDO 16 DGND 15 DGNDO 14 DOUT 13 SCLK
SPI and QSPI are a trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
TSSOP
Pin Configurations continued at end of data sheet. 1
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303
ABSOLUTE MAXIMUM RATINGS
AVDD1 to AGND1 ....................................................-0.3V to +6V AVDD2 to AGND2 ....................................................-0.3V to +6V DVDD to DGND ........................................................-0.3V to +6V DVDDO to DGNDO ..................................................-0.3V to +6V DVDD to DVDDO ......................................................-0.3V to +6V DVDD, DVDDO to AVDD1 ........................................-0.3V to +6V AVDD1, DVDD, DVDDO to AVDD2 ..........................-0.3V to +6V DGND, DGNDO, AGND3, AGND2 to AGND1 ......-0.3V to +0.3V CS, SCLK, DIN, DOUT, SSTRB to DGNDO ............................................-0.3V to (DVDDO + 0.3V) CH0-CH7 to AGND1 ...................................................-6V to +6V REF, REFCAP to AGND1.......................-0.3V to (AVDD1 + 0.3V) Continuous Current (any pin) ...........................................50mA Continuous Power Dissipation (TA = +70C) 20-Pin TSSOP (derate 11mW/C above +70C) ..........879mW 24-Pin TSSOP (derate 12.2mW/C above +70C) .......976mW Operating Temperature Range ...........................-40C to +85C Junction Temperature .....................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DC ACCURACY (Notes 1, 2) Resolution Integral Nonlinearity Differential Nonlinearity Transition Noise INL DNL MAX130_A MAX130_B No missing codes External or internal reference Single-ended inputs Offset Error Differential inputs (Note 3) Channel-to-Channel Gain Matching Channel-to-Channel Offset Error Matching Offset Temperature Coefficient Gain Error Gain Temperature Coefficient Unipolar Endpoint Overlap Unipolar or bipolar Unipolar or bipolar Unipolar Bipolar Unipolar Bipolar Unipolar Bipolar Negative unipolar full scale to positive unipolar zero-scale Differential inputs, FSR = 2 x VREF Signal-to-Noise Plus Distortion SINAD Single-ended inputs, FSR = VREF Single-ended inputs, FSR = VREF / 2 Single-ended inputs, FSR = VREF / 4 80 0 1.5 1.0 20 Unipolar Bipolar Unipolar Bipolar -1 1 0 -1.0 0 -2.0 0.025 1.0 10 5 0.5 0.3 10 10 20 20 %FSR mV ppm/C %FSR ppm/C LSB mV 16 1.0 1.0 2 4 +2 Bits LSB LSB LSBRMS SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC SPECIFICATIONS fIN(SINE-WAVE) = 5kHz, VIN = FSR - 0.05dB, fSAMPLE = 130ksps (Notes 1, 2) 90 88 85 82 dB
2
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8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS Differential inputs, FSR = 2 x VREF Signal-to-Noise Ratio SNR Single-ended inputs, FSR = VREF Single-ended inputs, FSR = VREF / 2 Single-ended inputs, FSR = VREF / 4 Total Harmonic Distortion (Up to the 5th Harmonic) Spurious-Free Dynamic Range Aperture Delay Aperture Jitter Channel-to-Channel Isolation CONVERSION RATE External clock mode, Figure 2 Byte-Wide Throughput Rate fSAMPLE External acquisition mode, Figure 3 Internal clock mode, Figure 4 ANALOG INPUTS (CH0-CH3 MAX1303, CH0-CH7 MAX1302, AGND1) Small-Signal Bandwidth Full-Power Bandwidth All input ranges, VIN = 100mVP-P (Note 2) All input ranges, VIN = 4VP-P (Note 2) R[2:1] = 001 R[2:1] = 010 R[2:1] = 011 Input Voltage Range (Table 6) VCH_ R[2:1] = 100 R[2:1] = 101 R[2:1] = 110 R[2:1] = 111 True-Differential Analog CommonMode Voltage Range Common-Mode Rejection Ratio Input Current Input Capacitance Input Resistance VCMDR CMRR ICH_ CCH_ RCH_ DIF/SGL = 1 DIF/SGL = 1, input voltage range = VREF / 4 -VREF < VCH_ < +VREF -1500 5 6 -VREF / 4 -VREF / 2 0 -VREF / 2 -VREF 0 -VREF -4.75 75 +650 1.5 700 +VREF / 4 0 +VREF / 2 +VREF / 2 0 +VREF +VREF +5.50 V dB A pF k V MHz kHz 114 84 106 ksps THD SFDR tAD tAJ Figure 21 Figure 21 92 MIN TYP 90 88 85 82 -98 99 15 100 105 dB dB ns ps dB dB MAX UNITS
MAX1302/MAX1303
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3
8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303
ELECTRICAL CHARACTERISTICS (continued)
(AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Reference Output Voltage Reference Temperature Coefficient Reference Short-Circuit Current Reference Load Regulation EXTERNAL REFERENCE (REFCAP = AVDD) Reference Input Voltage Range REFCAP Buffer Disable Threshold VREF VRCTH (Note 4) VREF = +4.096V, external clock mode, external acquisition mode, internal clock mode, or partial power-down mode VREF = +4.096V, full power-down mode External clock mode, external acquisition mode, internal clock mode, or partial power-down mode Full power-down mode DIGITAL INPUTS (DIN, SCLK, CS) Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUTS (DOUT, SSTRB) Output Low Voltage Output High Voltage DOUT Tri-State Leakage Current Analog Supply Voltage Digital Supply Voltage VOL VOH IDDO AVDD1 DVDD DVDDO = 4.75V, ISINK = 10mA DVDDO = 2.7V, ISINK = 5mA ISOURCE = 0.5mA CS = DVDDO DVDDO - 0.4 -10 4.75 4.75 +10 5.25 5.25 0.4 0.4 V V A V V VIH VIL VHYST IIN CIN VIN = 0 to DVDDO -10 10 0.2 +10 0.7 x DVDDO 0.3 x DVDDO V V V A pF 20 3.800 AVDD1 - 0.4 90 0.1 45 40 4.136 AVDD1 - 0.1 200 10 k M V V SYMBOL VREF TCREF IREFSC REF shorted to AGND1 REF shorted to AVDD IREF = 0 to 0.5mA CONDITIONS MIN 4.056 TYP 4.096 30 10 -1 0.1 10 MAX 4.136 UNITS V ppm/C mA mV
INTERNAL REFERENCE (Bypass REFCAP with 0.1F to AGND1 and REF with 1.0F to AGND1)
Reference Input Current
IREF
A
Reference Input Resistance
RREF
POWER REQUIREMENTS (AVDD1 and AGND1, AVDD2 and AGND2, DVDD and DGND, DVDDO and DGNDO)
4
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8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Preamplifier Supply Voltage Digital I/O Supply Voltage SYMBOL AVDD2 DVDDO External clock mode, Internal reference external acquisition mode, or internal External reference clock mode External clock mode, external acquisition mode, or internal clock mode External clock mode, external acquisition mode, or internal clock mode External clock mode, external acquisition mode, or internal clock mode Partial power-down mode Full power-down mode PSRR All analog input ranges External clock mode SCLK Period tCP External acquisition mode Internal clock mode External clock mode SCLK High Pulse Width (Note 5) tCH External acquisition mode Internal clock mode External clock mode SCLK Low Pulse Width (Note 5) DIN to SCLK Setup DIN to SCLK Hold SCLK Fall to DOUT Valid CS Fall to DOUT Enable tCL tDS tDH tDO tDV External acquisition mode Internal clock mode 272 228 100 109 92 40 109 92 40 40 0 40 40 ns ns ns ns ns ns CONDITIONS MIN 4.75 2.70 3 2.5 0.9 17.5 0.2 1.3 2 0.5 62 62 83 s TYP MAX 5.25 5.25 3.5 mA 3 2 25 1 mA mA mA mA A LSB UNITS V V
MAX1302/MAX1303
AVDD1 Supply Current
IAVDD1
DVDD Supply Current AVDD2 Supply Current DVDDO Supply Current Total Supply Current Power-Supply Rejection Ratio
IDVDD IAVDD2 IDVDDO
TIMING CHARACTERISTICS (Figures 15 and 16)
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5
8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303
ELECTRICAL CHARACTERISTICS (continued)
(AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER CS Rise to DOUT Disable CS Fall to SCLK Rise Setup CS High Minimum Pulse Width SCLK Fall to CS Rise Hold SSTRB Rise to CS Fall Setup DOUT Rise/Fall Time SSTRB Rise/Fall Time CL = 50pF CL = 50pF SYMBOL tTR tCSS tCSPW tCSH 40 40 0 40 10 10 CONDITIONS MIN TYP MAX 40 UNITS ns ns ns ns ns ns ns
Note 1: Note 2: Note 3: Note 4:
Parameter tested at AVDD1 = AVDD2 = DVDD = DVDDO = 5V. See definitions in the Parameter Definitions section at the end of the data sheet. Guaranteed by correlation with single-ended measurements. To ensure external reference operation, VREFCAP must exceed (AVDD1 - 0.1V). To ensure internal reference operation, VREFCAP must be below (AVDD1 - 0.4V). Bypassing REFCAP with a 0.1F or larger capacitor to AGND1 sets VREFCAP 4.096V. The transition point between internal reference mode and external reference mode lies between the REFCAP buffer disable threshold minimum and maximum values (Figures 17 and 18). Note 5: The SCLK duty cycle can vary between 40% and 60%, as long as the tCL and tCH timing requirements are met.
Typical Operating Characteristics
(AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (VREF), CDOUT = 50pF, CSSTRB = 50pF; unless otherwise noted.)
ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE
MAX1302/03 toc01
PREAMPLIFIER SUPPLY CURRENT vs. PREAMPLIFIER SUPPLY VOLTAGE
MAX1302/03 toc02
DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY VOLTAGE
EXTERNAL CLOCK MODE 0.85 TA = +85C TA = +25C
MAX1302/03 toc03
2.60 EXTERNAL CLOCK MODE 2.55 TA = +85C 2.50 IAVDD1 (mA)
24 EXTERNAL CLOCK MODE 23 22 21 IAVDD2 (mA) TA = +85C
0.90
IDVDD (mA)
2.45 2.40 2.35
TA = +25C
20 19 18 17 16 TA = -40C TA = +25C
0.80
0.75 TA = -40C 0.70
TA = -40C
2.30 4.75 4.85 4.95 5.05 5.15 5.25 AVDD1 (V)
15 4.75 4.85 4.95 5.05 5.15 5.25 AVDD2 (V)
0.65 4.75 4.85 4.95 5.05 5.15 5.25 DVDD (V)
6
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8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303
Typical Operating Characteristics (continued)
(AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (VREF), CDOUT = 50pF, CSSTRB = 50pF; unless otherwise noted.)
DIGITAL I/O SUPPLY CURRENT vs. DIGITAL I/O SUPPLY VOLTAGE
MAX1302/03 toc04
ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE
PARTIAL POWER-DOWN MODE 0.53 TA = +85C IAVDD1 (mA) 0.51 TA = +25C 0.49 TA = -40C 0.47
MAX1302/03 toc05
0.28 EXTERNAL CLOCK MODE 0.26 0.24 IDVDDO (mA) 0.22 0.20 0.18 0.16 0.14 0.12 0.10 4.75 4.85 4.95 5.05 5.15 TA = -40C TA = +85C TA = +25C
0.55
0.45 5.25 4.75 4.85 4.95 5.05 5.15 5.25 DVDDO (V) AVDD1 (V)
PREAMPLIFIER SUPPLY CURRENT vs. PREAMPLIFIER SUPPLY VOLTAGE
MAX1302/03 toc06
DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY VOLTAGE
PARTIAL POWER-DOWN MODE 0.134 0.132 IDVDD (mA) 0.130 0.128 0.126 0.124 TA = -40C TA = +25C 4.75 4.85 4.95 5.05 5.15 5.25 TA = +85C
MAX1302/03 toc07
0.20 PARTIAL POWER-DOWN MODE 0.18 IAVDD2 (mA) TA = +85C
0.136
0.16 TA = +25C 0.14 TA = -40C 0.12
0.122 0.10 4.75 4.85 4.95 5.05 5.15 5.25 AVDD2 (V) 0.120
DVDD (V)
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7
8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303
Typical Operating Characteristics (continued)
(AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (VREF), CDOUT = 50pF, CSSTRB = 50pF; unless otherwise noted.)
ANALOG SUPPLY CURRENT vs. CONVERSION RATE
MAX1302/03 toc08
PREAMPLIFIER SUPPLY CURRENT vs. CONVERSION RATE
fCLK = 7.5MHz (NOTE 6) 20 IAVDD2 (mA) EXTERNAL CLOCK MODE FULL POWER-DOWN MODE, PARTIAL POWER-DOWN MODE
MAX1302/03 toc09
3.0 2.5 2.0 IAVDD1 (mA) 1.5 1.0 0.5 0 0 50 100 150 200 CONVERSION RATE (ksps) PARTIAL POWER-DOWN MODE EXTERNAL CLOCK MODE
25
15
10
FULL POWER-DOWN MODE
5
0 0 50 100 150 200 CONVERSION RATE (ksps)
DIGITAL SUPPLY CURRENT vs. CONVERSION RATE
MAX1302/03 toc10
DIGITAL I/O SUPPLY CURRENT vs. CONVERSION RATE
fCLK = 7.5MHz (NOTE 6) 0.5 EXTERNAL CLOCK MODE IDVDDO (mA) 0.4 0.3 0.2
MAX1302/03 toc11
1.8 1.6 1.4 1.2 IDVDD (mA) 1.0 0.8 0.6 0.4 FULL POWER-DOWN MODE 0.2 0 0 50 100 150 200 CONVERSION RATE (ksps) EXTERNAL CLOCK MODE, PARTIAL POWER-DOWN MODE fCLK = 7.5MHz (NOTE 6)
0.6
0.1 0 0 50
FULL POWER-DOWN MODE, PARTIAL POWER-DOWN MODE 100 150 200
CONVERSION RATE (ksps)
Note 6:
For partial power-down and full power-down modes, external clock mode was used for a burst of continuous samples. Partial power-down or full power-down modes were entered thereafter. By using this method, the conversion rate was found by averaging the number of conversions over the time starting from the first conversion to the end of the partial power-down or full power-down modes.
8
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8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303
Typical Operating Characteristics (continued)
(AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (VREF), CDOUT = 50pF, CSSTRB = 50pF; unless otherwise noted.)
EXTERNAL REFERENCE INPUT CURRENT vs. EXTERNAL REFERENCE INPUT VOLTAGE
MAX1302/03 toc12
GAIN DRIFT vs. TEMPERATURE
MAX1302toc13
OFFSET DRIFT vs. TEMPERATURE
0.8 0.6 OFFSET ERROR (mV) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 VREF BIPOLAR +VREF/4 BIPOLAR RANGE
MAX1302toc14
0.16 ALL MODES EXTERNAL REFERENCE CURRENT (mA)
0.10 0.08 0.06 GAIN DRIFT (%) 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 VREF/4 BIPOLAR VREF BIPOLAR RANGE +VREF/2 BIPOLAR
1.0
0.15
0.14
0.13
0.12 3.80 3.85 3.90 3.95 4.00 4.05 4.10 4.15 EXTERNAL REFERENCE VOLTAGE (V)
-0.10 -40 -15 10 35 60 85 TEMPERATURE (C)
-40
-15
10
35
60
85
TEMPERATURE (C)
CHANNEL-TO-CHANNEL ISOLATION vs. INPUT FREQUENCY
MAX1302/03 toc15
COMMON-MODE REJECTION RATIO vs. FREQUENCY
MAX1302/03 toc16
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE
1.5 1.0 INL (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0 fSAMPLE = 115ksps VREF BIPOLAR RANGE
MAX1302toc17
0 -20 ISOLATION (dB) -40 fSAMPLE = 115ksps VREF BIPOLAR RANGE CH0 TO CH2
0 -10 -20 -30 CMRR (dB) -40 -50 -60 -70 -80 -90 fSAMPLE = 115ksps VREF BIPOLAR RANGE
2.0
-60 -80 -100 -120 1 10 100 FREQUENCY (kHz) 1000 10,000
-100 1 10 100 FREQUENCY (kHz) 1000 10,000
0
16,384
32,768
49,152
65,535
DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE
1.5 1.0 MAGNITUDE (dB) DNL (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0 0 16,384 32,768 49,152 65,535 DIGITAL OUTPUT CODE fSAMPLE = 115ksps VREF BIPOLAR RANGE
MAX1302toc18
FFT AT 5kHz
-20 -40 SNR, SINAD (dB) -60 -80 -100 -120 -140 0 10 20 30 40 50 TEMPERATURE (C) fSAMPLE = 115ksps fIN(SINE WAVE) = 5kHz VREF BIPOLAR RANGE
MAX1302toc19
SNR, SINAD, ENOB vs. ANALOG INPUT FREQUENCY
100 90 80 70 60 50 40 30 20 10 0 1 10 100 1000 FREQUENCY (kHz) fSAMPLE = 115ksps VREF BIPOLAR RANGE ENOB SNR SINAD
MAX1302/03 toc20
2.0
0
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9
8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303
Typical Operating Characteristics (continued)
(AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (VREF), CDOUT = 50pF, CSSTRB = 50pF; unless otherwise noted.)
SNR, SINAD, ENOB vs. SAMPLE RATE
100 SNR, SINAD 80 ENOB SNR, SINAD (dB) 60 12 -SFDR, THD (dB) ENOB (BITS) -40 -60 -80 -100 -120 0.1 1 10 SAMPLE RATE (ksps) 100 1000 THD -SFDR 6 14 -20
MAX1302/03 toc21
-SFDR, THD vs. SAMPLE RATE
fIN(SINE WAVE) = 5kHz VREF BIPOLAR RANGE
MAX1302/03 toc22
16
0
40
10
20 fIN(SINE WAVE) = 5kHz VREF BIPOLAR RANGE 0.1 1 10 SAMPLE RATE (ksps) 100 1000
8
0
-SFDR, THD vs. ANALOG INPUT FREQUENCY
MAX1302/03 toc23
ANALOG INPUT CURRENT vs. ANALOG INPUT VOLTAGE
MAX1302/03 toc24
0 -20 -SFDR, THD (dB) -40 -60 -80 -100 -120 1 10 100 THD -SFDR fSAMPLE = 115ksps VREF BIPOLAR RANGE
1.5 1.0 0.5 0 -0.5 -1.0 -1.5
ANALOG INPUT CURRENT (mA)
1000
-6
-4
-2
0
2
4
6
FREQUENCY (kHz)
ANALOG INPUT VOLTAGE (V)
SMALL-SIGNAL BANDWIDTH
MAX1302/03 toc25
0 -5 ATTENUATION (dB) -10 -15 -20 -25 -30 1 10 100 FREQUENCY (kHz) 1000
10,000
10
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8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303
Typical Operating Characteristics (continued)
(AVDD1 = AVDD2 = DVDD = DVDDO = 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (VREF), CDOUT = 50pF, CSSTRB = 50pF; unless otherwise noted.)
FULL-POWER BANDWIDTH
MAX1302/03 toc26
NOISE HISTOGRAM (CODE EDGE)
65,534 SAMPLES
MAX1302/03toc27
0 -10 ATTENUATION (dB) -20 -30 -40 -50 -60 1 10 100 FREQUENCY (kHz) 1000
35,000 30,000 NUMBER OF HITS 25,000 20,000 15,000 10,000 5000 0
10,000
32,769 32,770 32,771 32,772 32,773 32,774 CODE
NOISE HISTOGRAM (CODE CENTER)
65,534 SAMPLES 35,000 30,000 NUMBER OF HITS 25,000 20,000 15,000 10,000 5000 0 32,767 32,768 32,769 32,770 CODE 32,771 32,772 32,773
MAX11302/03 toc28
REFERENCE VOLTAGE vs. TIME
MAX1302/03 toc29
40,000
1V/div
0V
4ms/div
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11
8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303
Pin Description
PIN MAX1302 MAX1303 1 2 3 4 5 6 7 8 9 10 2 3 4 5 6 -- -- -- -- 7 NAME AVDD1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CS FUNCTION Analog Supply Voltage 1. Connect AVDD1 to a +4.75V to +5.25V power-supply voltage. Bypass AVDD1 to AGND1 with a 0.1F capacitor. Analog Input Channel 0 Analog Input Channel 1 Analog Input Channel 2 Analog Input Channel 3 Analog Input Channel 4 Analog Input Channel 5 Analog Input Channel 6 Analog Input Channel 7 Active-Low Chip-Select Input. When CS is low, data is clocked into the device from DIN on the rising edge of SCLK. With CS low, data is clocked out of DOUT on the falling edge of SCLK. When CS is high, activity on SCLK and DIN is ignored and DOUT is high impedance. Serial Data Input. When CS is low, data is clocked in on the rising edge of SCLK. When CS is high, transitions on DIN are ignored. Serial-Strobe Output. When using the internal clock, SSTRB rising edge transitions indicate that data is ready to be read from the device. When operating in external clock mode, SSTRB is always low. SSTRB does not tri-state, regardless of the state of CS, and therefore requires a dedicated I/O line. Serial Clock Input. When CS is low, transitions on SCLK clock data into DIN and out of DOUT. When CS is high, transitions on SCLK are ignored. Serial Data Output. When CS is low, data is clocked out of DOUT with each falling SCLK transition. When CS is high, DOUT is high impedance. Digital I/O Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together. Digital Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together. Digital I/O Supply Voltage Input. Connect DVDDO to a +2.7V to +5.25V power-supply voltage. Bypass DVDDO to DGNDO with a 0.1F capacitor. Digital-Supply Voltage Input. Connect DVDD to a +4.75V to +5.25V power-supply voltage. Bypass DVDD to DGND with a 0.1F capacitor.
11
8
DIN
12
9
SSTRB
13 14 15 16 17 18
10 11 12 13 14 15
SCLK DOUT DGNDO DGND DVDDO DVDD
19
16
Bandgap-Voltage Bypass Node. For external reference operation, connect REFCAP to AVDD. For REFCAP internal reference operation, bypass REFCAP with a 0.01F capacitor to AGND1 (VREFCAP 4.096V). Reference-Buffer Output/ADC Reference Input. For external reference operation, apply an external reference voltage from 3.800V to 4.136V to REF. For internal reference operation, bypassing REF with a 1F capacitor to AGND1 sets VREF = 4.096V 1%.
20
17
REF
12
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8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs
Pin Description (continued)
PIN MAX1300 MAX1301 21 22 23 24 18 19 20 1 NAME AGND3 AVDD2 AGND2 AGND1 FUNCTION Analog Signal Ground 3. AGND3 is the ADC negative reference potential. Connect AGND3 to AGND1. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together. Analog Supply Voltage 2. Connect AVDD2 to a +4.75V to +5.25V power-supply voltage. Bypass AVDD2 to AGND2 with a 0.1F capacitor. Analog Ground 2. This ground carries approximately five times more current than AGND1. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together. Analog Ground 1. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
5.0V 5.0V 5.0V
MAX1302/MAX1303
0.1F
0.1F
0.1F
AVDD2 CHO 4-20mA PLC ACCELERATION PRESSURE TEMPERATURE WHEATESTONE WHEATESTONE CH1 CH2 CH3 CH4 CH5 CH6 CH7 REF 1F 0.1F AGND1 REFCAP
AVDD1
DVDD DVDDO
3.3V VDD 0.1F MC68HCXX C SCK I/O MOSI I/O MISO VSS
MAX1302
SCLK CS DIN SSTRB DOUT
AGND2 AGND3
DGND
DGNDO
Figure 1. Typical Application Circuit
Detailed Description
The MAX1302/MAX1303 multirange, low-power, 16-bit successive-approximation ADCs operate from a single +5V supply and have a separate digital supply allowing digital interface with 2.7V to 5.25V systems. These 16-bit ADCs have internal track-and-hold (T/H) circuitry that supports single-ended and fully differential inputs. For single-ended conversions, the valid analog input voltage range spans from -VREF below ground to +VREF above ground. The maximum allowable differential input voltage spans from -2 x VREF to +2 x VREF. Data can be converted in a variety of software-programmable channel and data-acquisition configurations. Microprocessor (P) con-
trol is made easy through an SPI-/QSPI-/MICROWIREcompatible serial interface. The MAX1302 has eight single-ended analog input channels or four differential channels (see the Block Diagram at the end of the data sheet). The MAX1303 has four single-ended analog input channels or two differential channels. Each analog input channel is independently software programmable for seven single-ended input ranges (0 to +VREF/2, -VREF/2 to 0, 0 to +VREF, -VREF to 0, VREF/4, VREF/2, and VREF) and three differential input ranges (VREF/2, VREF, and 2 x VREF). Additionally, all analog input channels are fault tolerant to 6V. A fault condition on an idle channel does not affect the conversion result of other channels.
13
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8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303
Power Supplies
To maintain a low-noise environment, the MAX1302 and MAX1303 provide separate power supplies for each section of circuitry. Table 1 shows the four separate power supplies. Achieve optimal performance using separate AVDD1, AVDD2, DVDD, and DVDDO supplies. Alternatively, connect AV DD1 , AV DD2 , and DV DD together as close to the device as possible for a convenient power connection. Connect AGND1, AGND2, AGND3, DGND, and DGNDO together as close to the device as possible. Bypass each supply to the corresponding ground using a 0.1F capacitor (Table 1). If significant low-frequency noise is present, add a 10F capacitor in parallel with the 0.1F bypass capacitor.
Track-and-Hold Circuitry
The MAX1302/MAX1303 feature a switched-capacitor T/H architecture that allows the analog input signal to be stored as charge on sampling capacitors. See Figures 2, 3, and 4 for T/H timing and the sampling instants for each operating mode. The MAX1302/MAX1303 analog input circuitry buffers the input signal from the sampling capacitors, resulting in a constant analog input impedance with varying input voltage (Figure 5).
Analog Input Circuitry
Select differential or single-ended conversions using the associated analog input configuration byte (Table 2). The analog input signal source must be capable of driving the ADC's 6k input resistance (Figure 6). Figure 6 shows the simplified analog input circuit. The analog inputs are 6V fault tolerant and are protected by back-to-back diodes. The summing junction voltage, VSJ, is a function of the channel's input common-mode voltage:
R1 R1 VSJ = x VCM x 2.375V + 1 + R1 + R2 R1 + R2
Converter Operation
The MAX1302/MAX1303 ADCs feature a fully differential, successive-approximation register (SAR) conversion technique and an on-chip T/H block to convert voltage signals into a 16-bit digital result. Both singleended and differential configurations are supported with programmable unipolar and bipolar signal ranges.
Table 1. MAX1302/MAX1303 Power Supplies and Bypassing
POWER SUPPLY/GROUND DVDDO/DGNDO AVDD2/AGND2 AVDD1/AGND1 DVDD/DGND SUPPLY VOLTAGE RANGE (V) 2.7 to 5.25 4.75 to 5.25 4.75 to 5.25 4.75 to 5.25 TYPICAL SUPPLY CURRENT (mA) 0.2 17.5 3.0 0.9 CIRCUIT SECTION Digital I/O Analog Circuitry Analog Circuitry Digital Control Logic and Memory BYPASSING 0.1F to DGNDO 0.1F to AGND2 0.1F to AGND1 0.1F to DGND
Table 2. Analog Input Configuration Byte
BIT NUMBER 7 6 5 4 NAME START C2 C1 C0 Differential or Single-Ended Configuration Bit. DIF/SGL = 0 configures the selected analog input channel for single-ended operation. DIF/SGL = 1 configures the channel for differential operation. In single-ended mode, input voltages are measured between the selected input channel and AGND1, as shown in Table 4. In differential mode, the input voltages are measured between two input channels, as shown in Table 5. Be aware that changing DIF/SGL adjusts the FSR, as shown in Table 6. Channel-Select Bits. SEL[2:0] select the analog input channel to be configured (Tables 4 and 5). DESCRIPTION Start Bit. The first logic 1 after CS goes low defines the beginning of the analog input configuration byte.
3
DIF/SGL
2 1 0
R2 R1 R0 Input-Range-Select Bits. R[2:0] select the input voltage range, as shown in Table 6 and Figure 7.
14
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8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303
CS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
SCLK
BYTE 1
BYTE 2
BYTE 3
BYTE 4
SSTRB
DIN
S
C2
C1
C0
0
0
0
0 fSAMPLE fSCLK / 32
SAMPLING INSTANT tACQ ANALOG INPUT TRACK AND HOLD* HOLD TRACK HOLD
DOUT
HIGH IMPEDANCE
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
HIGH IMPEDANCE
*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.
Figure 2. External Clock-Mode Conversion (Mode 0)
As a result, the analog input impedance is relatively constant over the input voltage as shown in Figure 5. Single-ended conversions are internally referenced to AGND1 (Tables 3 and 4). In differential mode, IN+ and IN- are selected according to Tables 3 and 5. When configuring differential channels, the differential pair follows the analog configuration byte for the positive channel. For example, to configure CH2 and CH3 for a VREF differential conversion, set the CH2 analog configuration byte for a differential conversion with the VREF range (1010 1100). To initiate a conversion for the CH2 and CH3 differential pair, issue the command 1010 0000.
Analog Input Bandwidth
The MAX1302/MAX1303 input-tracking circuitry has a 1.5MHz small-signal bandwidth. The 1.5MHz input bandwidth makes it possible to digitize high-speed transient events. Harmonic distortion increases when digitizing signal frequencies above 15kHz as shown in the THD, SFDR vs. Analog Input Frequency plot in the Typical Operating Characteristics.
Analog Input Range and Fault Tolerance
Figure 7 illustrates the software-selectable singleended analog input voltage range that produces a valid digital output. Each analog input channel can be independently programmed to one of seven single-ended input ranges by setting the R[2:0] control bits with DIF/SGL = 0.
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15
8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303
CS
SSTRB
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
SCLK
BYTE 1
BYTE 2
BYTE 3
BYTE 4
DIN
S
C2
C1
C0
0
0
0
0
DOUT
HIGH IMPEDANCE
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
fSAMPLE fSCLK / 32 + fINTCLK / 17
SAMPLING INSTANT tACQ ANALOG INPUT TRACK AND HOLD* HOLD TRACK HOLD
100ns to 400ns
14
15
16
17
1
2
3
INTCLK**
fINTCLK 4.5MHz *TRACK AND HOLD TIMING IS CONTROLLED BY SCLK. **INTCLK IS AN INTERNAL SIGNAL AND IS NOT ACCESSIBLE TO THE USER.
Figure 3. External Acquisition-Mode Conversion (Mode 1)
Figure 8 illustrates the software-selectable differential analog input voltage range that produces a valid digital output. Each analog input differential pair can be independently programmed to one of three differential input ranges by setting the R[2:0] control bits with DIF/SGL = 1. Regardless of the specified input voltage range and whether the channel is selected, each analog input is 6V fault tolerant. The analog input fault protection is active whether the device is unpowered or powered.
Any voltage beyond FSR, but within the 6V fault-tolerant range, applied to an analog input results in a fullscale output voltage for that channel. Clamping diodes with breakdown thresholds in excess of 6V protect the MAX1302/MAX1303 analog inputs during ESD and other transient events (Figure 6). The clamping diodes do not conduct during normal device operation, nor do they limit the current during such transients. When operating in an environment with the potential for high-energy voltage and/or current transients, protect the MAX1302/MAX1303 externally.
16
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8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303
CS
SSTRB
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
9
1
2
3
4
5
6
7
8
SCLK
BYTE 1
BYTE 2
BYTE 3
DIN
S
C2
C1
C0
0
0
0
0
DOUT
HIGH IMPEDANCE fSAMPLE fSCLK / 24 + fINTCLK / 28 SAMPLING INSTANT tACQ
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
ANALOG INPUT TRACK AND HOLD*
HOLD
TRACK
HOLD
100ns to 400ns
10
11
12
13
14
25
26
27
28
1
2
3
INTCLK**
fINTCLK 4.5MHz *TRACK AND HOLD TIMING IS CONTROLLED BY INTCLK, AND IS NOT ACCESSIBLE TO THE USER. **INTCLK IS AN INTERNAL SIGNAL AND IS NOT ACCESSIBLE TO THE USER.
Figure 4. Internal Clock-Mode Conversion (Mode 2)
1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -6 -4 -2 0 2 4 6 ANALOG INPUT VOLTAGE (V)
MAX1302 MAX1303
*RSOURCE ANALOG SIGNAL SOURCE IN_+ R1
R2
ANALOG INPUT CURRENT (mA)
VSJ R2
*RSOURCE ANALOG SIGNAL SOURCE
IN_+
R1
VSJ
*MINIMIZE RSOURCE TO AVOID GAIN ERROR AND DISTORTION.
Figure 5. Analog Input Current vs. Input Voltage
Figure 6. Simplified Analog Input Circuit 17
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8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303
Table 3. Input Data Word Formats
DATA BIT OPERATION Conversion-Start Byte (Tables 4 and 5) Analog-Input Configuration Byte (Table 2) Mode-Control Byte (Table 7) D7 (START) 1 1 1 D6 C2 C2 M2 D5 C1 C1 M1 D4 C0 C0 M0 D3 0 DIF/SGL 1 D2 0 R2 0 D1 0 R1 0 D0 0 R0 0
Table 4. Channel Selection in Single-Ended Mode (DIF/SGL = 0)
CHANNEL-SELECT BIT C2 0 0 0 0 1 1 1 1 C1 0 0 1 1 0 0 1 1 C0 0 1 0 1 0 1 0 1 CH0 + + + + + + + + CH1 CH2 CH3 CHANNEL CH4 CH5 CH6 CH7 AGND1 -
Table 5. Channel Selection in True-Differential Mode (DIF/SGL = 1)
CHANNEL-SELECT BIT C2 0 0 0 0 1 1 1 1 C1 0 0 1 1 0 0 1 1 C0 0 1 0 1 0 1 0 1 RESERVED + RESERVED + RESERVED + CH0 + CH1 RESERVED CH2 CH3 CHANNEL CH4 CH5 CH6 CH7 AGND1
Differential Common-Mode Range
The MAX1302/MAX1303 differential common-mode range (VCMDR) must remain within -4.75V to +5.5V to obtain valid conversion results. The differential common-mode range is defined as: VCMDR =
In addition to the common-mode input voltage limitations, each individual analog input must be limited to 6V with respect to AGND1. The range-select bits R[2:0] in the analog input configuration bytes determine the full-scale range for the corresponding channel (Tables 2 and 6). Figures 9, 10, and 11 show the valid analog input voltage ranges for the MAX1302/MAX1303 when operating with FSR = VREF/2, FSR = VREF, and FSR = 2 x VREF, respectively.
(CH _ +) + (CH _ -)
2
18
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8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303
+VREF +2 x VREF +3/2 VREF FSR = VREF
+3/4 VREF
+VREF/2 FSR = VREF / 2
+VREF
(CH_+) - (CH_-) (V)
(CH_) - AGND1 (V)
+VREF/4 FSR = VREF / 2
+VREF/2 FSR = 2 x VREF FSR = 4 x VREF 101 110 111 FSR = VREF 001
FSR = 2 x VREF
FSR = VREF
0
0
-VREF/4
FSR = VREF / 2
-VREF/2
-VREF/2 -3/4 VREF
FSR = VREF
-VREF
-3/2 VREF
001
010
011
100
101
110
111
010
011
INPUT RANGE SELECTION BITS, R[2:0] EACH INPUT IS FAULT TOLERANT TO 6V.
INPUT RANGE SELECTION BITS, R[2:0] EACH INPUT IS FAULT TOLERANT TO 6V.
Figure 7. Single-Ended Input Voltage Ranges
Figure 8. Differential Input Voltage Ranges
The shaded area contains the valid common-mode voltage ranges that support the entire FSR.
Digital Interface
The MAX1302/MAX1303 feature a serial interface that is compatible with SPI/QSPI and MICROWIRE devices. DIN, DOUT, SCLK, CS, and SSTRB facilitate bidirectional communication between the MAX1302/MAX1303 and the master at SCLK rates up to 10MHz (internal clock mode, mode 2), 3.67MHz (external clock mode, mode 0), or 4.39MHz (external acquisition mode, mode 1). The master, typically a microcontroller, should use the CPOL = 0, CPHA = 0, SPI transfer format, as shown in the timing diagrams of Figures 2, 3, and 4. The digital interface is used to: * Select single-ended or true-differential input channel configurations * Select the unipolar or bipolar input range * Select the mode of operation: External clock (mode 0) External acquisition (mode 1) Internal clock (mode 2) Reset (mode 4) Partial power-down (mode 6) Full power-down (mode 7) * Initiate conversions and read results
Chip Select (CS) CS enables communication with the MAX1302/MAX1303. When CS is low, data is clocked into the device from DIN on the rising edge of SCLK and data is clocked out of DOUT on the falling edge of SCLK. When CS is high, activity on SCLK and DIN is ignored and DOUT is high impedance allowing DOUT to be shared with other peripherals. SSTRB is never high impedance and therefore cannot be shared with other peripherals. Serial Strobe Output (SSTRB) As shown in Figures 3 and 4, the SSTRB transitions high to indicate that the ADC has completed a conversion and results are ready to be read by the master. SSTRB remains low in the external clock mode (Figure 2) and consequently may be left unconnected. SSTRB is driven high or low regardless of the state of CS, therefore SSTRB cannot be shared with other peripherals.
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100
-VREF
-2 x VREF
19
8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303
Table 6. Range-Select Bits
DIF/SGL 0 0 R2 0 0 R1 0 0 R0 0 1 MODE No Range Change* Single-Ended Bipolar -VREF/4 to +VREF/4 Full-Scale Range (FSR) = VREF / 2 Single-Ended Unipolar -VREF/2 to 0 FSR = VREF / 2 Single-Ended Unipolar 0 to +VREF/2 FSR = VREF / 2 Single-Ended Bipolar -VREF/2 to +VREF/2 FSR = VREF Single-Ended Unipolar -VREF to 0 FSR = VREF Single-Ended Unipolar 0 to +VREF FSR = VREF DEFAULT SETTING Single-Ended Bipolar -VREF to +VREF FSR = 2 x VREF No Range Change** Differential Bipolar -VREF/2 to +VREF/2 FSR = VREF Reserved Reserved Differential Bipolar -VREF to +VREF FSR = 2 x VREF Reserved Reserved Differential Bipolar -2 x VREF to +2 x VREF FSR = 4 x VREF TRANSFER FUNCTION -- Figure 12
0
0
1
0
Figure 13
0
0
1
1
Figure 14
0
1
0
0
Figure 12
0
1
0
1
Figure 13
0
1
1
0
Figure 14
0
1
1
1
Figure 12
1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
-- Figure 12 -- -- Figure 12 -- -- Figure 12
*Conversion-Start Byte (see Table 3). **Mode-Control Byte (see Table 3).
20
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8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303
6 4 2 0 -2 -4 VREF = 4.096V -6 -8 -6 -4 -2 0 2 4 6 8 INPUT VOLTAGE (V) -6 -8 -6 -4 -2 0 2 4 6 8 INPUT VOLTAGE (V) 6 4 2 0 -2 -4 VREF = 4.096V COMMON-MODE VOLTAGE (V) COMMON-MODE VOLTAGE (V) VREF = 4.096V -6 -8 -6 -4 -2 0 2 4 6 8 INPUT VOLTAGE (V)
Figure 9. Common-Mode Voltage vs. Input Voltage (FSR = VREF)
6 4 2 0 -2 -4
Figure 10. Common-Mode Voltage vs. Input Voltage (FSR = 2 x VREF)
COMMON-MODE VOLTAGE (V)
Output Data Format Output data is clocked out of DOUT in offset binary format on the falling edge of SCLK, MSB first (B15). For output binary codes, see the Transfer Function section and Figures 12, 13, and 14. Configuring Analog Inputs Each analog input has two configurable parameters: * Single-ended or true-differential input * Input voltage range These parameters are configured using the analog input configuration byte as shown in Table 2. Each analog input has a dedicated register to store its input configuration information. The timing diagram of Figure 15 shows how to write to the analog input configuration registers. Figure 16 shows DOUT and SSTRB timing.
Figure 11. Common-Mode Voltage vs. Input Voltage (FSR = 4 x VREF)
Start Bit Communication with the MAX1302/MAX1303 is accomplished using the three input data word formats shown in Table 3. Each input data word begins with a start bit. The start bit is defined as the first high bit clocked into DIN with CS low when any of the following are true: * Data conversion is not in process and all data from the previous conversion has clocked out of DOUT. * The device is configured for operation in external clock mode (mode 0) and previous conversion-result bits B15-B3 have clocked out of DOUT. * The device is configured for operation in external acquisition mode (mode 1) and previous conversionresult bits B15-B7 have clocked out of DOUT. * The device is configured for operation in internal clock mode, (mode 2) and previous conversionresult bits B15-B4 have clocked out of DOUT.
Transfer Function
An ADC's transfer function defines the relationship between the analog input voltage and the digital output code. Figures 12, 13, and 14 show the MAX1302/ MAX1303 transfer functions. The transfer function is determined by the following characteristics: * Analog input voltage range * Single-ended or differential configuration * Reference voltage The axes of an ADC transfer function are typically in least significant bits (LSBs). For the MAX1302/MAX1303, an LSB is calculated using the following equation: 1 LSB = FSR x VREF
2N x 4.096V where N is the number of bits (N = 16) and FSR is the full-scale range (see Figures 7 and 8).
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8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303
FSR FFFF FFFE FFFD BINARY OUTPUT CODE (LSB [hex]) BINARY OUTPUT CODE (LSB [hex]) FFFF FFFE FFFD FSR
8000 7FFF
FSR
8000 7FFF
0003 0002 0001 0000 -32,768 -32,766 -1 0 +1 +32,765 +32,767 1 LSB = FSR x VREF 65,536 x 4.096V
0003 0002 0001 0000 0 1 2 3 32,768 INPUT VOLTAGE (LSB [DECIMAL]) AGND1 (DIF/SGL = 0) 0V (DIF/SGL = 1) INPUT VOLTAGE (LSB [DECIMAL]) (AGND1) 65,533 65,535 1 LSB = FSR x VREF 65,536 x 4.096V
Figure 13. Ideal Unipolar Transfer Function, Single-Ended Input, -FSR to 0
Figure 12. Ideal Bipolar Transfer Function, Single-Ended or Differential Input
FSR FFFF FFFE FFFD BINARY OUTPUT CODE (LSB [hex])
8001 8000 7FFF FSR
Selecting the Conversion Method The conversion method is selected using the mode-control byte (see the Mode Control section), and the conversion is initiated using a conversion start command (Table 3, and Figures 2, 3, and 4).The MAX1302/MAX1303 convert analog signals to digital data using one of three methods: * External Clock Mode, Mode 0 (Figure 2) * Highest maximum throughput (see the Electrical Characteristics table) * User controls the sample instant * CS remains low during the conversion * User supplies SCLK throughout the ADC conversion and reads data at DOUT External Acquisition Mode, Mode 1 (Figure 3) * Lowest maximum throughput (see the Electrical Characteristics table) * User controls the sample instant * User supplies two bytes of SCLK, then drives CS high to relieve processor load while the ADC converts * After SSTRB transitions high, the user supplies two bytes of SCLK and reads data at DOUT Internal Clock Mode, Mode 2 (Figure 4) * High maximum throughput (see the Electrical Characteristics table) * The internal clock controls the sampling instant
0003 0002 0001 0000 0 1 2 3 32,768 INPUT VOLTAGE (LSB [DECIMAL]) (AGND1) 65,533 65,535 1 LSB = FSR x VREF 65,536 x 4.096V
*
Figure 14. Ideal Unipolar Transfer Function, Single-Ended Input, 0 to +FSR
Mode Control
The MAX1302/MAX1303 contain one byte-wide modecontrol register. The timing diagram of Figure 15 shows how to use the mode-control byte, and the mode-control byte format is shown in Table 7. The mode-control byte is used to select the conversion method and to control the power modes of the MAX1302/MAX1303.
22
*
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FSR
8001
8001
8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303
tCSS CS tCL SCLK tDS DIN START SEL2 SEL1 SEL0 1 tCP DIF/SGL R2 R1 tCH tCSH 8 tDH R0 START M2 M1 M0 1 0 0 0 1 8 tCSPW
ANALOG INPUT CONFIGURATION BYTE tDV DOUT HIGH IMPEDANCE tTR HIGH IMPEDANCE
MODE CONTROL BYTE
HIGH IMPEDANCE
Figure 15. Analog Input Configuration Byte and Mode-Control Byte Timing
SSTRB tSSCS CS tCSS SCLK tDO DOUT HIGH IMPEDANCE MSB
NOTE: SSTRB AND CS REMAIN LOW IN EXTERNAL CLOCK MODE (MODE 0).
External Clock Mode (Mode 0) The MAX1302/MAX1303's fastest maximum throughput rate is achieved operating in external clock mode. SCLK controls both the acquisition and conversion of the analog signal, facilitating precise control over when the analog signal is captured. The analog input sampling instant is at the falling edge of the 14th SCLK (Figure 2). Since SCLK drives the conversion in external clock mode, the SCLK frequency should remain constant while the conversion is clocked. The minimum SCLK frequency prevents droop in the internal sampling capacitor voltages during conversion. SSTRB remains low in the external clock mode, and as a result may be left unconnected if the MAX1302/ MAX1303 will always be used in the external clock mode.
Figure 16. DOUT and SSTRB Timing
* User supplies one byte of SCLK, then drives CS high to relieve processor load while the ADC converts * After SSTRB transitions high, the user supplies two bytes of SCLK and reads data at DOUT
Table 7. Mode-Control Byte
BIT NUMBER 7 6 5 4 3 2 1 0 BIT NAME START M2 M1 M0 1 0 0 0 Bit 3 must be a logic 1 for the mode-control byte. Bit 2 must be a logic 0 for the mode-control byte. Bit 1 must be a logic 0 for the mode-control byte. Bit 0 must be a logic 0 for the mode-control byte. Mode-Control Bits. M[2:0] select the mode of operation as shown in Table 8. DESCRIPTION Start Bit. The first logic 1 after CS goes low defines the beginning of the mode-control byte.
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8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303
Table 8. Mode-Control Bits M[2:0]
M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 External Clock (DEFAULT) External Acquisition Internal Clock Reserved Reset Reserved Partial Power-Down Full Power-Down MODE
External Acquisition Mode (Mode 1) The slowest maximum throughput rate is achieved with the external acquisition method. SCLK controls the acquisition of the analog signal in external acquisition mode, facilitating precise control over when the analog signal is captured. The internal clock controls the conversion of the analog input voltage. The analog input sampling instant is at the falling edge of the 16th SCLK (Figure 3). For the external acquisition mode, CS must remain low for the first 15 clock cycles and then rise on or after the falling edge of the 16th SCLK cycle as shown in Figure 3. For optimal performance, idle DIN and SCLK during the conversion. With careful board layout, transitions at DIN and SCLK during the conversion have a minimal impact on the conversion result. After the conversion is complete, SSTRB asserts high and CS can be brought low to read the conversion result. SSTRB returns low on the rising SCLK edge of the subsequent start bit. Internal Clock Mode (Mode 2) In internal clock mode, the internal clock controls both acquisition and conversion of the analog signal. The internal clock starts approximately 100ns to 400ns after the falling edge of the eighth SCLK and has a rate of about 4.5MHz. The analog input sampling instant occurs at the falling edge of the 11th internal clock signal (Figure 4). For the internal clock mode, CS must remain low for the first seven SCLK cycles and then rise on or after the falling edge of the eighth SCLK cycle. After the conversion is complete, SSTRB asserts high and CS can be brought low to read the conversion result. SSTRB returns low on the rising SCLK edge of the subsequent start bit.
Reset (Mode 4) As shown in Table 8, set M[2:0] = 100 to reset the MAX1302/MAX1303 to its default conditions. The default conditions are full power operation with each channel configured for VREF, bipolar, single-ended conversions using external clock mode (mode 0). Partial Power-Down Mode (Mode 6) As shown in Table 8, when M[2:0] = 110, the device enters partial power-down mode. In partial powerdown, all analog portions of the device are powered down except for the reference voltage generator and bias supplies. To exit partial power-down, change the mode by issuing one of the following mode-control bytes (see the Mode Control section): * External-clock-mode control byte * External-acquisition-mode control byte * Internal-clock-mode control byte * Reset byte * Full power-down-mode control byte This prevents the MAX1302/MAX1303 from inadvertently exiting partial power-down mode because of a CS glitch in a noisy digital environment. Full Power-Down Mode (Mode 7) When M[2:0] = 111, the device enters full power-down mode and the total supply current falls to 1A (typ). In full power-down, all analog portions of the device are powered down. When using the internal reference, upon exiting full power-down mode, allow 10ms for the internal reference voltage to stabilize prior to initiating a conversion. To exit full power-down, change the mode by issuing one of the following mode-control bytes (see the Mode Control section): * External-clock-mode control byte
24
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8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs
* External-acquisition-mode control byte * Internal-clock-mode control byte * Reset byte * Partial power-down-mode control byte This prevents the MAX1302/MAX1303 from inadvertently exiting full power-down mode because of a CS glitch in a noisy digital environment. REF. When using the internal reference, bypass REFCAP with a 0.1F or greater capacitor to AGND1 and bypass REF with a 1.0F or greater capacitor to AGND1. External Reference For external reference operation, disable the internal reference and reference buffer by connecting REFCAP to AV DD1 . With AV DD1 connected to REFCAP, REF becomes a high-impedance input and accepts an external reference voltage. The MAX1302/MAX1303 external reference current varies depending on the applied reference voltage and the operating mode (see the External Reference Input Current vs. External Reference Input Voltage in the Typical Operating Characteristics).
MAX1302/MAX1303
Power-On Reset
The MAX1302/MAX1303 power up in normal operation configured for external clock mode with all circuitry active (Tables 7 and 8). Each analog input channel (CH0-CH7) is set for single-ended conversions with a VREF bipolar input range (Table 6). Allow the power supplies to stabilize after power-up. Do not initiate any conversions until the power supplies have stabilized. Additionally, allow 10ms for the internal reference to stabilize when CREF = 1.0F and CRECAP = 0.1F. Larger reference capacitors require longer stabilization times.
Applications Information
Noise Reduction
Additional samples can be taken and averaged (oversampling) to remove the effect of transition noise on conversion results. The square root of the number of samples determines the improvement in performance. For example, with 2/3 LSB RMS (4 LSBP-P) transition noise, 16 (42 = 16) samples must be taken to reduce the noise to 1 LSBP-P.
Internal or External Reference
The MAX1302/MAX1303 operate with either an internal or external reference. The reference voltage impacts the ADC's FSR (Figures 12, 13, and 14). An external reference is recommended if more accuracy is required than the internal reference provides, and/or multiple converters require the same reference voltage. Internal Reference The MAX1302/MAX1303 contain an internal 4.096V bandgap reference. This bandgap reference is connected to REFCAP through a nominal 5k resistor (Figure 17). The voltage at REFCAP is buffered creating 4.096V at
Interface with 4-20mA Signals
Figure 19 illustrates a simple interface between the MAX1302/MAX1303 and a 4-20mA signal. 4-20mA signaling can be used as a binary switch (4mA represents a logic-low signal, 20mA represents a logic-high signal), or for precision communication where currents between 4mA and 20mA represent intermediate analog data. For binary switch applications, connect the 4-20mA signal to the MAX1302/MAX1303 with a resistor to ground. For example, a 200 resistor converts the 4-20mA signal to a 0.8V to 4V signal. Adjust the resistor value so the parallel combination of the resistor and the MAX1302/MAX1303 source impedance is 200. In this application, select the single-ended 0 to VREF range (R[2:0] = 011, Table 6). For applications that require precision measurements of continuous analog currents between 4mA and 20mA, use a buffer to prevent the MAX1302/MAX1303 input from diverting current from the 4-20mA signal.
SAR ADC REF
4.096V
REF 1.0F
1x
MAX1302 MAX1303
5k
REFCAP 0.1F VRCTH
4.096V BANDGAP REFERENCE
AGND1
Figure 17. Internal Reference Operation ______________________________________________________________________________________ 25
8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303
V+
IN SAR ADC REF 4.096V REF 1.0F OUT
1.0F
MAX6341
1x AVDD1 REFCAP GND
MAX1302 MAX1303
5k
VRCTH 4.096V BANDGAP REFERENCE
AGND1
Figure 18. External Reference Operation
Bridge Application
The MAX1302/MAX1303 convert 1kHz signals more accurately than a similar sigma-delta converter that might be considered in bridge applications. The input impedance of the MAX1302, in combination with the current-limiting resistors, can affect the gain of the MAX1302. In many applications this error is acceptable, but for applications that cannot tolerate this error, the MAX1302 inputs can be buffered (Figure 20). Connect the bridge to a low-offset differential amplifier and then the true differential inputs of the MAX1302/MAX1303. Larger excitation voltages take advantage of more of the VREF/2 differential input voltage range. Select an input voltage range that matches the amplifier output. Be aware of the amplifier offset and offset-drift errors when selecting an appropriate amplifier.
Layout, Grounding, and Bypassing
Careful PC board layout is essential for best system performance. Boards should have separate analog and digital ground planes and ensure that digital and analog signals are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the device package. Figure 1 shows the recommended system ground connections. Establish an analog ground point at AGND1 and a digital ground point at DGND. Connect all analog grounds to the star analog ground. Connect the digital grounds to the star digital ground. Connect the digital ground plane to the analog ground plane at one point. For lowest noise operation, make the ground return to the star ground's power-supply low impedance and as short as possible. High-frequency noise in the AV DD1 power supply degrades the ADC's high-speed comparator performance. Bypass AVDD1 to AGND1 with a 0.1F ceramic surface-mount capacitor. Make bypass capacitor connections as short as possible.
Dynamically Adjusting the Input Range
Software control of each channel's analog input range and the unipolar endpoint overlap specification make it possible for the user to change the input range for a channel dynamically and improve performance in some applications. Changing the input range results in a small LSB step-size over a wider output voltage range. For example, by switching between a -VREF/2 to 0V range and a 0 to VREF/2 range, an LSB is: (VREF / 2) x VREF 65, 536 x 4.096 but the input voltage range effectively spans from -VREF/2 to +VREF/2 (FSR = +VREF).
Parameter Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer function from a straight line. This straight line is either a best straight-line fit or a line drawn between the endpoints of the transfer function once offset and gain errors have been nullified. The MAX1302/MAX1303 INL is measured using the endpoint method.
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8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303
4-20mA INPUT CH0 C
200
MAX1302
4-20mA INPUT CH8
200
Figure 19. 4-20mA Application
LOW-OFFSET DIFFERENTIAL AMPLIFIER
CH0 CH1
P
MAX1302 MAX1303
REF
BRIDGE
Figure 20. Bridge Application
Differential Nonlinearity (DNL)
DNL is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of greater than -1 LSB guarantees no missing codes and a monotonic transfer function.
Channel-to-Channel Isolation
Channel-to-channel isolation indicates how well each analog input is isolated from the others. The channel-tochannel isolation for these devices is measured by applying a near full-scale magnitude 5kHz sine wave to the selected analog input channel while applying an equal magnitude sine wave of a different frequency to all unselected channels. An FFT of the selected channel output is used to determine the ratio of the magnitudes of the signal applied to the unselected channels and the 5kHz signal applied to the selected analog input channel. This ratio is reported, in dB, as channelto-channel isolation.
Transition Noise
Transition noise is the amount of noise that appears at a code transition on the ADC transfer function. Conversions performed with the analog input right at the code transition can result in code flickering in the LSBs.
______________________________________________________________________________________
27
8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303
Unipolar Offset Error
-FSR to 0V When a zero-scale analog input voltage is applied to the converter inputs, the digital output is all ones (0xFFFF). Ideally, the transition from 0xFFFF to 0xFFFE occurs at AGND1 - 0.5 LSB. Unipolar offset error is the amount of deviation between the measured zero-scale transition point and the ideal zero-scale transition point, with all untested channels grounded. 0V to +FSR When a zero-scale analog input voltage is applied to the converter inputs, the digital output is all zeros (0x0000). Ideally, the transition from 0x0000 to 0x0001 occurs at AGND1 + 0.5 LSB. Unipolar offset error is the amount of deviation between the measured zero-scale transition point and the ideal zero-scale transition point, with all untested channels grounded. Full-Power Bandwidth A 95% of full-scale sine wave is applied to the ADC, and the input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. Common-Mode Rejection Ratio (CMRR) CMRR is the ability of a device to reject a signal that is "common" to or applied to both input terminals. The common-mode signal can be either an AC or a DC signal or a combination of the two. CMR is expressed in decibels. Common-mode rejection ratio is the ratio of the differential signal gain to the common-mode signal gain. CMRR applies only to differential operation. Power-Supply Rejection Ratio (PSRR) PSRR is the ratio of the output-voltage shift to the power-supply-voltage shift for a fixed input voltage. For the MAX1302/MAX1303, AVDD1 can vary from 4.75V to 5.25V. PSRR is expressed in decibels and is calculated using the following equation:
5.25V - 4.75V PSRR[dB] = 20 x log VOUT (5.25V) - VOUT (4.75V)
Bipolar Offset Error
When a zero-scale analog input voltage is applied to the converter inputs, the digital output is a one followed by all zeros (0x8000). Ideally, the transition from 0x7FFF to 0x8000 occurs at (2N-1 - 0.5) LSB. Bipolar offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point, with untested channels grounded. Gain Error When a positive full-scale voltage is applied to the converter inputs, the digital output is all ones (0xFFFF). The transition from 0xFFFE to 0xFFFF occurs at 1.5 LSB below full scale. Gain error is the amount of deviation between the measured full-scale transition point and the ideal full-scale transition point with the offset error removed and all untested channels grounded. Unipolar Endpoint Overlap Unipolar endpoint overlap is the change in offset when switching between complementary input voltage ranges. For example, the difference between the voltage that results in a 0xFFFF output in the -VREF/2 to 0V input voltage range and the voltage that results in a 0x0000 output in the 0 to +VREF/2 input voltage range is the unipolar endpoint overlap. The unipolar endpoint overlap is positive for the MAX1302/MAX1303, preventing loss of signal or a dead zone when switching between adjacent analog input voltage ranges. Small-Signal Bandwidth A 100mVP-P sine wave is applied to the ADC, and the input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB.
For the MAX1302/MAX1303, PSRR is tested in bipolar operation with the analog inputs grounded.
Aperture Jitter
Aperture jitter, tAJ, is the statistical distribution of the variation in the sampling instant (Figure 21).
Aperture Delay
Aperture delay, tAD, is the time from the falling edge of SCLK to the sampling instant (Figure 21).
Signal-to-Noise Ratio (SNR)
SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset. SignalRMS SINAD(dB) = 20 x log NoiseRMS
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8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs
Effective Number of Bits (ENOB)
ENOB indicates the global accuracy of an ADC at a specific input frequency and sampling rate. With an input range equal to the ADC's full-scale range, calculate the ENOB as follows: SINAD - 1.76 ENOB = 6.02
SCLK (MODE 0) 13 14 15
MAX1302/MAX1303
SCLK (MODE 1)
15
16
INTCLK (MODE 2)
10
11
12
Total Harmonic Distortion (THD)
For the MAX1302/MAX1303, THD is the ratio of the RMS sum of the input signal's first four harmonic components to the fundamental itself. This is expressed as: V2 2 + V3 2 + V4 2 + V5 2 THD = 20 x log V1
ANALOG INPUT TRACK AND HOLD TRACK tAJ tAD SAMPLE INSTANT
HOLD
Figure 21. Aperture Diagram
where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonic components.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest spectral component.
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29
8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs MAX1302/MAX1303
Block Diagram
DVDDO CS DIN SSTRB DOUT SCLK DGNDO DVDD FIFO DGND AVDD1 AGND3
CONTROL LOGIC AND REGISTERS
SERIAL I/O
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 AGND1
AVDD2 ANALOG INPUT MUX AND MULTIRANGE CIRCUITRY CLOCK PGA IN SAR ADC REF AGND2 4.096V BANDGAP REFERENCE 5k 1x OUT
MAX1302
REFCAP REF
AVDD2 AGND2
Pin Configurations (continued)
TOP VIEW
AGND1 1 AVDD1 2 CH0 3 CH1 4 CH2 5 CH3 6 CS 7 DIN 8 SSTRB 9 SCLK 10 20 AGND2 19 AVDD2 18 AGND3 17 REF
Chip Information
TRANSISTOR COUNT: 28,210 PROCESS: BiCMOS
MAX1303
16 REFCAP 15 DVDD 14 DVDDO 13 DGND 12 DGNDO 11 DOUT
TSSOP
30
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8-/4-Channel, VREF Multirange Inputs, Serial 16-Bit ADCs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX1302/MAX1303
PACKAGE OUTLINE, TSSOP 4.40mm BODY
21-0066
G
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
TSSOP4.40mm.EPS

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